1. Field of the Invention
The present invention relates to a solid-state imaging apparatus and an imaging apparatus.
Priority is claimed on Japanese Patent Application No. 2012-175948, filed Aug. 8, 2012, the content of which is incorporated herein by reference.
2. Description of Related Art
Recently, imaging apparatuses such as video cameras and electronic still cameras have become popular. In these imaging apparatuses (hereinafter referred to as “cameras”), a charge coupled device (CCD) type solid-state imaging apparatus and an amplification type solid-state imaging apparatus are used. In the amplification type solid-state imaging apparatus, a plurality of pixels are disposed in a two-dimensional matrix shape. Accordingly, the amplification type solid-state imaging apparatus guides signal charges generated and accumulated by the photoelectric conversion section provided within a pixel on which light is incident to an amplification section provided within the pixel, and outputs a signal amplified by the amplification section as an output signal from the pixel.
An example of the amplification type solid-state imaging apparatus is a solid-state imaging apparatus using a junction field effect transistor in the amplification section, a complementary metal oxide semiconductor (CMOS) type solid-state imaging apparatus using a CMOS transistor in the amplification section, or the like.
In addition, in the related art, a scheme of sequentially reading signal charges generated and accumulated by the photoelectric conversion section of each pixel arranged in a two-dimensional matrix shape by row is adopted in a general CMOS type solid-state imaging apparatus (hereinafter referred to as “solid-state imaging apparatus”). In this read scheme, the timing of exposure in the photoelectric conversion section of each pixel is specified by the start and end of reading of signal charges, and an exposure timing of a pixel differs for every row.
As an exposure method, a simultaneous imaging function (hereinafter referred to as “global shutter function”) of implementing the simultaneity of generation and accumulation of signal charges by exposing all pixels at the same timing is proposed. Accordingly, the use of the CMOS type solid-state imaging apparatus having the global shutter function is increasing.
In the CMOS type solid-state imaging apparatus having the global shutter function, it is generally necessary to have a storage capacitance section with a light blocking effect so as to accumulate signal charges generated by the photoelectric conversion section until a read operation ends. In the CMOS type solid-state imaging apparatus of the related art having the above-described global shutter function, signal charges generated by photoelectric conversion sections after all pixels have been simultaneously exposed are transferred to storage capacitance sections simultaneously in all pixels and temporarily accumulated. Thereafter, the signal charges accumulated in the storage capacitance section are sequentially converted into a pixel signal at a predetermined read timing and the pixel signal is read.
A solid-state imaging apparatus in which a MOS image sensor chip in which a micro-pad is formed on a wiring layer side for every unit cell and a signal processing chip in which a micro-pad is formed on a wiring layer side of a position corresponding to the micro-pad of the MOS image sensor chip are connected through a micro-bump has been disclosed (see Japanese Unexamined Patent Application, First Publication No. 2006-49361). In addition, a method of preventing an increase in a chip area of a solid-state imaging apparatus by bonding a first substrate on which a photoelectric conversion section is formed with a second substrate on which a plurality of MOS transistors are formed has been disclosed (see Japanese Unexamined Patent Application, First Publication No. 2010-219339). Even in the technology disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-219339, the separately manufactured first and second substrates are electrically connected through a connection electrode.
In the technology disclosed in Japanese Unexamined Patent Application, First Publication No. 2006-49361, a cell of a MOS image sensor chip includes a photoelectric conversion element, an amplification transistor, and the like (see FIGS. 5 and 12 of Japanese Unexamined Patent Application, First Publication No. 2006-49361), and a cell of a signal processing chip has a configuration in which a signal output from the cell of the MOS image sensor chip is digitalized and stored in a memory (see FIGS. 8 and 9 of Japanese Unexamined Patent Application, First Publication No. 2006-49361).
In addition, in the technology disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-219339, circuit elements constituting a pixel having the global shutter function of the related art are divided and disposed on two substrates (see FIG. 9 of Japanese Unexamined Patent Application, First Publication No. 2010-219339). Thus, an increase of a chip area can be avoided. In addition, because a phenomenon of noise moving from the MOS image sensor chip to the signal processing chip due to light incident on a pixel during a waiting period until signal charges accumulated in the storage capacitance section of the MOS image sensor chip are read is suppressed by forming a configuration in which first and second substrates are bonded, it is possible to prevent signal quality from being deteriorated due to the above-described noise.